1. Field of the Invention
The present invention relates to a method for saving power in a computer. More particularly, the present invention relates to a method for conserving power by monitoring the central processing unit (CPU) of a computer system and dynamically adjusting the internal clock frequency, or internal operating voltage, of the CPU based on a perceived CPU processing load.
2. Description of the Prior Art
In order to conserve electricity, especially in laptop computer systems, various power-saving methods are used. These may include monitor timeouts, hard disk spin downs, and the computer entering a xe2x80x9csleepxe2x80x9d state after a period of inactivity. On certain processor systems, it is also possible to adjust the operating clock frequency, or internal operating voltage, of the central processing unit (CPU). When the processor runs at slower clock speeds, or lower voltages, it requires less power. As a significant amount of power is consumed by the CPU, reducing clock speeds and voltages is a reasonable strategy to extend operational time when running off a battery. For many of the most common applications, a CPU running at a reduced speed is usually sufficiently fast to not incur any inconvenience for the user.
The current method used to set the power saving modes of a computer involves accessing a power management program. This program may be accessed through a BIOS (Basic Input Output System) setup program, or through the operating system. In either case, to efficiently utilize and conserve power under various operating conditions, the user must set appropriate power-saving parameters. As most people do not enjoy adjusting such system internals, they tend to set the processor speed to its highest value and leave it at that. On laptop systems, this can cause an unnecessary loss of battery time.
It is therefore a primary objective of this invention to provide an autonomous means of monitoring the processing load of the CPU. Based upon a perceived processing load of the CPU, the internal clock frequency of the CPU is adjusted accordingly to reduce the electrical power consumed by the CPU.
The present invention, briefly summarized, calls for a monitoring circuit that is electrically connected to the CPU. This circuit monitors the state of a memory access line on the CPU, as there is a strong correlation between the state of this line and the processing load of the CPU. The monitoring circuit can interrupt the processor to force an interrupt service call to a BIOS routine. This BIOS routine will adjust the internal clock frequency and operating voltage of the CPU based upon the perceived processing load of the CPU.
By using a circuit to autonomously monitor the perceived processing load of the CPU, the internal clock frequency and operating voltage of the CPU can be adjusted to ensure that applications run as quickly as possible, while using as little energy as possible.